Low loss integrated circuit with reduced clock swing

ABSTRACT

The integrated circuit with a clock system, particularly a CMOS circuit with extensive pipelining, whereby an optimally low overall dissipated power is effected in that a clock driver circuit is provided with a specifically wired driver output stage that generates a clock supply voltage that corresponds to about half the value of a general supply voltage. A great reduction of the dissipated power can be achieved given relative slight sacrifices in the performance capability.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a clock circuit for anintegrated circuit which reduces power consumption.

2. Description of the Related Art

The reduction of the dissipated power becomes more and more importantdue to the constantly increasing complexity of VLSI circuits, on the onehand, and the greater and greater employment of such components inbattery-operated mobile devices and systems as well. Particularly inintegrated CMOS circuits with many registers, a considerable part of thedissipated power devolves onto the recharging of the capacitance of theclock node or, in systems with distributed clocks, the clock nodes.Between 30 and 50 percent of the overall dissipated power thereby oftenarises in the clock system.

The overall capacitance of the clock node is composed of the gatecapacitances of the transistors connected to the clock nodes and of thewiring capacitances of the clock lines. The two components cannot simplybe arbitrarily reduced. Even increasingly smaller structures as a resultof technological progress do not solve this problem since the lateraldimensions of a gate and of a line are in fact reduced, but theinsulation layer also becomes thinner at the same time, and the smallerlateral dimensions are used for accommodating even more functions on agiven chip area. Added thereto is that, given metal tracks with a widthon the order of magnitude of 1 μm, the capacitance already dominates dueto the edge capacitance and the coupling capacitance and is thus definednearly only by the length of the line. A reduction of the track widthleaves the edge capacitance nearly unmodified and does not significantlyreduce the overall capacitance; a reduction of the interconnect spacingincreases the coupling capacitance and, thus, the overall capacitance aswell.

Given the fundamental assumption that the data throughput rate of thesystem should remain unaltered, a reduction of the switching frequencyrequires an increased complexity (parallelization), so that no saving ofdissipated power can be achieved overall.

Another possibility of reducing the dissipated power is comprised inlowering the supply voltage of the overall circuit, whereby the supplyvoltage even enters quadratically into the dissipated power but requiresa loss-affected matching to other circuit parts and potentially causes areduction of the immunity to interference.

The publication PATENT ABSTRACT OF JAPAN, Volume 14, No.346 (DevelopmentBoundary Conditions-956) 4289! for Japanese Application JP-A-2 119427discloses an output buffer circuit whereby further transistors forlimiting the output amplitude are connected in series between the supplyvoltage terminals (VDD, VSS) and the respective output transistors, andthe occurrence of malfunctions is avoided in this way.

The publication International Patent Application WO-A-92 009 141discloses a differential output buffer circuit whose two branches arerespectively wired with terminals of the full supply voltage (VDD, VSS),and the branches respectively comprise a series circuit of outputtransistors and an additional MOS limiting transistor, whereby the gatesof the MOS limiting transistors are driven with a voltage generated in abias generator that is lower than the full supply voltage.

SUMMARY OF THE INVENTION

An object underlying the invention is to provide an integrated circuitthat has an optimally good relationship between the reduction of theoverall dissipated power and the reduction of the performance capabilityand immunity to interference connected therewith. This and other objectis inventively achieved by an integrated circuit arrangement having aclock driver circuit, a first terminal of at least a last stage of theclock driver circuit being supplied with a clock supply voltage that islower in terms of amount than a general supply voltage of the integratedcircuit, whereby a second terminal of the at least one last stage of theclock driver circuit is directly connected to reference potential, andwhereby a load current flows between the first and second terminal. Thepreferred embodiments provide an integrated circuit wherein the laststage of the clock driver circuit is supplied by an external voltagesource. The clock supply voltage is generated from the general supplyvoltage by a series controller, one terminal of the series controllerbeing connected to the last stage of the clock driver circuit and afurther terminal of the series controller being connected to the generalvoltage supply.

A switching transistor is provided, the first terminal thereof beingconnected to the general supply voltage, the second terminal thereofbeing connected to the general clock supply voltage and the gateterminal thereof being supplied with a clock signal inverse to the clockinput signal of the last stage; and whereby the second terminal of theswitching transistor is connected to reference potential via anauxiliary capacitor.

An inverter unit is provided that is supplied with the differencevoltage between the output of the last stage and the general supplyvoltage, that is driven with a clock input signal inverse to the clockinput signal of the last stage, and whose output supplies the clocksupply voltage for the last driver stage, whereby the clock supplyvoltage simultaneously represents a clock output signal inverse to aclock output signal of the last stage. The clock supply voltage is setsuch that the value of the clock supply voltage amounts to 0.4 through0.6 times the value of the general supply voltage The advantages of thepreferred embodiments derive from the following comments.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in greater detail below with reference todrawings. There shown are:

FIG. 1 is a circuit diagram of a first exemplary embodiment of a circuitpart critical to the invention;

FIG. 2 is a circuit diagram of a second exemplary embodiment of thecircuit part critical to the invention;

FIG. 3 is a circuit diagram of a third exemplary embodiment of thecircuit part critical to the invention; and

FIG. 4 is a circuit diagram of a last exemplary embodiment of theinventive circuit part of the low-loss integrated circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

What are to be particularly understood as low-loss integrated circuitsin this context are CMOS circuits. CMOS circuits with extensivepipelining are thereby particularly envisioned, since these comprise aseries of registers and, thus, a more extensive clock system as a rule.

The fundamental idea is comprised in the employment of a clock generatoror, respectively, a clock driver with reduced swing, i.e. that thesupply voltage of the clock driver is reduced by the factor r comparedto the general supply voltage. The basic structure of the clock drivercomprises series-connected inverter units whose transistor widthsincrease toward the clock driver output. For achieving a reduced clockswing, it suffices when only the last inverter unit at the clock driveroutput is modified.

FIG. 1 shows a first exemplary embodiment of the driver unit at theclock driver output. For example, two complementary switchingtransistors SP and SN are thereby connected in series, whereby a firstterminal of the transistor SP is connected to an externally existing,reduced clock supply voltage VHH and a first terminal of the transistorSN is connected to reference potential VSS, the second terminals of thetransistors SP and SN are connected to one another and the gateterminals of the transistors SP and SN are respectively supplied with anoutput signal Phi_(in) of a preceding inverter unit. A load capacitorC_(Load) at which the clock output signal Phi_(out) is adjacent liesbetween the connection of the two transistors SP and SN and referencepotential VSS. The external clock supply voltage VHH is reduced by thefactor r compared to the general supply voltage VDD.

Two external clock supply voltages are required for applications withcomplementary clock phases if the swing in the clock system is notsupposed to be VDD/2. The maximally possible reduction of the dissipatedpower in the clock system thereby ensues, whereby a reduction by thefactor r² occurs. However, it must also be taken into consideration thatthe dissipated power in the regulators of the additional, externalsupply voltage is added to the internal dissipated power of the chip.

FIG. 2 shows a further example of the driver unit at the clock driveroutput, this differing from FIG. 1 only in that the clock supply voltageV, instead of being an external clock supply VHH, is generated with theassistance of a voltage controller VC. For example, the voltagecontroller VC can thereby be composed of a classic series regulator asemployed, for example in stabilized power pack parts. The dissipatedpower in the clock driver circuit is thereby likewise reduced by thefactor r² ; however, the additional dissipated power in the controlcircuit VC at which the voltage (1-r)*VDD drops off must also be takeninto consideration, so that a reduction by only the factor r derivesoverall.

FIG. 3 shows a third exemplary embodiment of the driver unit at theoutput of the clock driver circuit. The controller VC shown in FIG. 2 isthereby replaced by a switching transistor SP1, whereby a first terminalof the transistor SP1 is supplied with the supply voltage VDD, a secondterminal is supplied with reference potential VSS via an auxiliarycapacitor C_(Dummy) and the gate terminal of the transistor SP1 issupplied with a clock signal PhiQ_(in) inverse to the clock input signalPhi_(in). The external auxiliary capacitor C_(Dummy) is charged during afirst clock phase, whereby the switching transistor SP1 inhibits. In theclock phase following thereupon, the load capacitor C_(Load) of theclock driver is charged from the auxiliary capacitor via the pull-uptransistor SP of the inverter unit. The swing is thereby determinedaccording to the following equation:

    V.sub.High =VDD ×C.sub.Dummy /(C.sub.Dummy +C.sub.Load).

For the specific case of C_(Dummy) =C_(Load) , a swing of VDD/2derivesin the clock system. The dissipated power is likewise reduced only bythe factor r.

As seen only from the point of view of the dissipated power reaction,the circuit therefore offers no advantage over the control circuit VC inFIG. 2.

In some cases, the external load capacitors that are required representtoo high an outlay. On the other hand, it is possible to freely selectthe clock swing in almost arbitrarily via this capacitor in that theexternal wiring is merely modified. Moreover, the charging of theauxiliary capacitor via the switching transistor SP1 can ensue with alonger time constant than the edge duration required in the clocksystem. Concretely, this means that the switching transistor forcharging the auxiliary capacitor can be dimensioned with a clearlysmaller transistor width than the pull-up transistor SP of the clockdriver output stage. In this way, the typical current peaks in thesupply system for the voltage VDD as produced by conventional clockdrivers can be reduced together with all their problematical sideeffects.

FIG. 4 shows a fourth and last embodiment of the driver unit at theclock driver output. The exemplary embodiment shown in FIG. 4 differsfrom the exemplary embodiment in FIG. 3 in that the auxiliary capacitorC_(Dummy) is replaced by a further load capacitor C_(Load) -Q whosesecond terminal is connected to the general supply voltage VDD and notto reference potential VSS, and in that a switching transistor SN1complementary to the switching transistor SP1 is provided, the firstterminal thereof being connected to the line for the reduced clocksupply voltage V, the second terminal thereof being connected to thejunction between the two transistors SP and SN and the gate thereofbeing connected to the gate of the transistor SP1.

Advantageously, the clock supply voltage (V) can be simultaneously usedas an output signal PhiQ_(out) inverse to the output signal Phi_(out) ofthe last stage.

The circuit embodiment of FIG. 4 likewise works according to theprinciple of charge division without, however, employing an additional,external capacitor. Instead, the charge is divided between the loadcapacitors of the two complementary clock drivers SP, SN and SP1, SN1.The circuit is employable for complementary clock systems, this beingespecially attractive in view of the dissipated power because simpleregisters can be employed. As in the exemplary embodiment of FIG. 3, thefactor r is defined by the capacitance ratios. The circuit of FIG. 4,however, is customized for the specific case of r=approx. 0.5. Since noadditional components are employed in this case for the reduction of thevoltage but the two complementary drivers mutually assume the role ofthe "drop resistor" for one another, a reduction of the dissipated powerby the factor r² thereby derives. Of all of the exemplary embodimentsthat have been considered, this is the only embodiment withoutadditional, external supply voltages wherein the dissipated power isreduced by the factor r², i.e. by the maximum reduction factor.

The reduction factor can be fundamentally selected in the range 0<r<1. Arange of about 0.4 through about 0.6 is optimum for employment in theintegrated circuit since a favorable relationship between dissipatedpower and performance capability or, respectively, immunity tointerference is thereby present.

The switching transistors Sp and SP1 can thereby be composed, forexample, of p-channel field effect transistors, and the switchingtransistors SN, SN1 can be composed of n-channel field effecttransistors but, for example, can also be realized in the form ofcorresponding npn and pnp transistors.

The reduction of signal swings must be basically considered in view of apotential reduction of the signal-to-noise ratio. When the swing isreduced for only a few signals within a chip, circuit parts at whichthese signals are adjacent become more susceptible to interference. Inknown circuits of this type, the full swing between VDD and VSS istherefore employed. Particularly given circuits with extensivepipelining, however, the clock system forms a certain exception sincethe clock nodes have a capacitance that is higher by orders of magnitudethan all other signal nodes occurring on the chip. At the same time, thetransistors in the output stage of the clock driver are dimensionedwider by orders of magnitude than in a normal output of a gate thatdrives some signal or other. The clock system therefore has an impedancethat is lower by orders of magnitude than all other signals lines at thechip. The clock signal can thus also not be as easily disturbed by aparasitic input such as, for example, some other signal power. Addedthereto is that signal networks that spread extremely far beyond thechip are coupled with a great number of other signals, this alsospecifically applying to clock networks. When it is assumed that thesesignals do not all simultaneously switch into one direction, the sum ofall these inputs becomes extremely small on average and approaches zeroin the limit value. This assumption of statistically uniformdistribution is definitely justified in normally integrated circuits ofthis type. Given completely dynamic logic circuits with pre-chargingstrategies that should not be considered here, of course, thisassumption no longer applies. Given standard integrated circuits of thistype, thus, the coupling of signals onto the lines of the clock systemis not very serious.

Given integrated circuits with registers, the switching time isgenerally increased due to the reduction of the signal swing. Without aredimensioning of the registers and given a reduction factor of r=0.5,the maximum switching frequency is reduced by 60% and the dissipatedpower in the clock network is reduced by 75%. The balance betweenswitching frequency and savings in dissipated power does not seemespecially advantageous at first sight; however, it must be taken intoconsideration that the maximum clock frequency of the system in manyapplications is not determined by the switching speed of the registersbut by critical paths in logic blocks.

On the basis of a redimensioning of the registers for instances whereina 60% reduction of the switching speed of the registers seemsunacceptable if, for example, the data throughput rate were to bediminished, the switching speed of the registers can be adapted byredimensioning the transistors driven by the clock. In order to achievethe same speed with a clock swing reduced by the factor r=0.5 as in thecase of swing that is not reduced, the transistor widths of thetransistors driven by the clock must be raised by about the factor 2.The overall capacitance of the system is thus increased. Since, however,the wiring capacitances are clearly higher than the capacitance derivingdue to the transistor gates, the overall capacitance of the clock systemis only slightly changed. The saving of dissipated power in the clocksystem can therefore still amount to up to 70% given a redimensioning ofthe registers.

Although other modifications and changes may be suggested by thoseskilled in the art, it is the intention of the inventors to embodywithin the patent warranted hereon all changes and modifications asreasonably and properly come within the scope of their contribution tothe art.

We claim:
 1. An integrated circuit, comprising:a clock driver circuit having first and second terminals and a plurality of stages,said first terminal of at least a last stage of the clock driver circuit being supplied with a clock supply voltage that is lower in terms of amount than a general supply voltage of the integrated circuit, said second terminal of the at least one last stage of the clock driver circuit being directly connected to reference potential, a load current flowing between said first and second terminals, an inverter unit being provided that is supplied with a difference voltage between an output of the last stage and the general supply voltage, that is driven with a clock input signal inverse to the clock input signal of the last stage, and said inverter having an output supplying the clock supply voltage for the last driver stage, the clock supply voltage simultaneously representing a clock output signal inverse to a clock output signal of the last stage.
 2. An integrated circuit according to claim 1, wherein the clock supply voltage is set such that a value of the clock supply voltage amounts to 0.4 through 0.6 times a value of the general supply voltage. 